1. Field of the Invention
Embodiments of the present invention relate to a multi-stage phase mixer circuit, and more particularly, to a technology for equalizing phase differences between two adjacent output clock signals generated by performing a phase mixing operation with respect to two or more input clock signals through a multi-stage process including two or more stages.
2. Description of the Related Art
In an integrated circuit chip, a phase mixer is frequently used to accomplish desirable characteristics such as a seamless boundary switching in a phase locked loop (PLL) or a delayed locked loop (DLL) that synchronizes a chip internal clock signal with an external clock signal.
A phase mixer refers to a device that receives two clock signals having the same frequency and different phases and mixes the received clock signals. The phase mixer outputs a clock signal having the same frequency as the two input clock signals and a phase between the phases of the two input clock signals through the phase mixing operation. A weight may be applied to adjust the phase of the output clock to a value close to one of the phases of the two input clock signals. For example, when the weight is 0, the phase of the output clock signal may be equalized to the phase of one input clock signal, and when the weight is 1, the phase of the output clock signal may be equalized to the phase of the other input clock signal.
FIG. 1 is a circuit diagram of a conventional phase mixer circuit 100. The phase mixer circuit of FIG. 1 includes three inverters 110, 120, and 130, and is configured to receive first and second input clock signals In1 and In2, respectively, and generate an output clock signal Out. The first and second inverters 110 and 120 have input terminals to receive the first and second input clock signals In1 and In2, respectively, and output terminals shorted to each other to perform a mixing operation. The first and second inverters 110 and 120 also respectively receive the weight control codes C<1:N> and C<1:N> having a complementary relationship with each other. Here, the weight control code C<1:N> indicates a binary code value composed of N-bit binary numbers, and the weight control code C<1:N> is composed of N-bit inverted binary numbers of the weight control code C<1:N>. For example, when N is 3 and C<1:N> is “0 0 0”, C<1:N> becomes “1 1 1”. An input terminal of the third inverter 130 is coupled to a common output terminal of the first and second inverters 110 and 120, and an output terminal of the third inverter 130 is used as an output terminal Out of the phase mixer.
FIG. 2 illustrates that, when N is 3, an output waveform Out of the phase mixer is changed depending on the weight control codes C<1:N> and C<1:N>. For example, when the binary code values of the weight control codes C<1:3> and C<1:3> are (‘0 0 0’, ‘1 1 1’), the output waveform Out of the phase mixer is identical to that of the first input clock signal In1. Then, as the binary code values are increased one by one, the output waveform Out of the phase mixer continues moving toward the input waveform of the second input clock signal In2. When the binary code values of the weights C<1:3> and C<1:3> reach (‘1 1 1’, ‘0 0 0’), the output waveform Out of the phase mixer becomes identical to the waveform of the second input clock signal In2.
In general, it is desirable that a phase mixer has an equal delay difference between two adjacent output clock signals corresponding to two successive N-bit binary numbers of a weight control code, in order to increase a resolution of the output clock signal while reducing jitter. As illustrated in FIG. 2, however, it can be seen that delay differences between the two adjacent output clock signals are not equal to each other due to a drivability difference between pull-up and pull-down units of the first and second inverters 110 and 120, but the output waveforms converge toward an intermediate value of the weight control code. That is, the phase difference between the adjacent output clock signals around the intermediate value of the weight control code is smaller than that around the minimum or maximum value of the weight control code.